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Support MIPS atomic on pre-MIPS32 architectures 

The atomic functions on MIPS are based on the sync opcode with an
immediate argument, which is something introduced in the MIPS32
instruction set. This prevent to use Qt on pre-MIPS32 CPU, like the
Loongson 2 CPU.

However some of the pre-MIPS32 CPUs interprets the sync opcode with and
immediate argument as a sync opcode without argument (which is a stronger
ordering than with the argument), and for the others the kernel emulates
it.

It is therefore fine to use the current MIPS atomic functions on
pre-MIPS32 CPU. This patch allows that by temporarily changing the
instruction set to MIPS32 around the sync instruction, so that binutils
doesn't choke on it.

Change-Id: I9cc984bd55b5f172736ce9e638a6f4e271b79fe7
Reviewed-by: Lisandro Damián Nicanor Pérez Meyer <perezmeyer@gmail.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
bb10
Aurelien Jarno 2013-11-10 23:20:46 +01:00 committed by Thiago Macieira
parent dd91f8d46d
commit 60b6b28c21
1 changed files with 8 additions and 2 deletions
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10
src/corelib/arch/qatomic_mips.h
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@ -110,13 +110,19 @@ template <typename T> struct QAtomicOps : QBasicAtomicOps<sizeof(T)>
template <int size> template <typename T> inline
void QBasicAtomicOps<size>::acquireMemoryFence(const T &) Q_DECL_NOTHROW
{
asm volatile ("sync 0x11" ::: "memory");
asm volatile (".set push\n"
".set mips32\n"
"sync 0x11\n"
".set pop\n" ::: "memory");
}
template <int size> template <typename T> inline
void QBasicAtomicOps<size>::releaseMemoryFence(const T &) Q_DECL_NOTHROW
{
asm volatile ("sync 0x12" ::: "memory");
asm volatile (".set push\n"
".set mips32\n"
"sync 0x11\n"
".set pop\n" ::: "memory");
}
template <int size> template <typename T> inline