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Fix the instruction of RISC-V arch that yield CPU 

Replace fence with pause in opcode form,
as GCC doesn't support fence operand.
Amends a7f227f56c.
Remove the builtin pause checking,
as in GCC13 this will always pass,
while the opcode pause works
regardless of the pause extension.

Task-number: QTBUG-103014
Pick-to: 6.7
Change-Id: I26e3c3b9f7d234be24abe1570aaf4c8cb3a272b3
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
bb10
Alex Bu 2024-02-21 14:15:11 +02:00
parent ec9ca7ac43
commit 61bd614abe
1 changed files with 1 additions and 3 deletions
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4
src/corelib/thread/qyieldcpu.h
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@ -51,10 +51,8 @@ void qYieldCpu(void)
#elif defined(Q_PROCESSOR_ARM) && Q_PROCESSOR_ARM >= 7 && defined(Q_CC_GNU)
asm("yield"); // this works everywhere
#elif __has_builtin(__builtin_riscv_pause)
__builtin_riscv_pause(); // Zihintpause extension
#elif defined(Q_PROCESSOR_RISCV)
asm("fence w, 0"); // a.k.a. "pause"
asm(".word 0x0100000f"); // a.k.a. "pause"
#elif defined(_YIELD_PROCESSOR) && defined(Q_CC_GHS)
_YIELD_PROCESSOR; // Green Hills (INTEGRITY), but only on ARM