qHash: update the pre-AVX512 mask to use the cacheline size
No change in behavior. But instead of trying to guess if we're going to cross a page boundary, we check for the cacheline: if we don't cross a cacheline boundary, then we can't cross a page boundary either. Testing bit 4 can be implemented with a shorter instruction than a test for bit 11. f43de: 40 f6 c7 20 test $0x20,%dil Change-Id: I664b9f014ffc48cbb49bfffd17b04817a0fb8c6b Reviewed-by: Mårten Nordheim <marten.nordheim@qt.io>bb10
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55959aefab
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fff9f5047a
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@ -756,16 +756,16 @@ aeshash128_lt16(__m128i state0, const __m128i *src, const __m128i *srcend, size_
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// including NULLs at the end because the length is in the key)
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// WARNING: this may produce valgrind warnings, but it's safe
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constexpr quintptr PageSize = 4096;
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constexpr quintptr CachelineSize = 64;
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__m128i data;
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if ((quintptr(src) & (PageSize / 2)) == 0) {
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// lower half of the page:
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if ((quintptr(src) & (CachelineSize / 2)) == 0) {
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// lower half of the cacheline:
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__m128i mask = _mm_loadu_si128(reinterpret_cast<const __m128i *>(maskarray + 15 - len));
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data = loadu128<ZX>(src);
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data = _mm_and_si128(data, mask);
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} else {
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// upper half of the page:
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// upper half of the cacheline:
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__m128i control = _mm_loadu_si128(reinterpret_cast<const __m128i *>(shufflecontrol + 15 - len));
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data = loadu128<ZX>(advance<ZX>(srcend, -1));
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data = _mm_shuffle_epi8(data, control);
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