Port the IA-64 atomics to the new QBasicAtomicXXX architecture

The IA-64 architecture supports the actual memory ordering semantics
in many instructions, but not all. We actually implement the functions
for all operations, so we get the best possible output.

It does support proper load-acquire and store-release semantics, but
we don't need instructions for it: the ABI requires that a volatile
load be acquire and a volatile store be release.

The Intel and HP compiler codepaths are rewritten, but untested.

Change-Id: I7aa62a4ec65f63a97d1bbd8418bb2492c2be465f
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>

src/corelib/arch/qatomic_arch.h

@@ -58,8 +58,6 @@ QT_BEGIN_HEADER
 #  include "QtCore/qatomic_bfin.h"
 #elif defined(QT_ARCH_GENERIC)
 #  include "QtCore/qatomic_generic.h"
-#elif defined(QT_ARCH_IA64)
-#  include "QtCore/qatomic_ia64.h"
 #elif defined(QT_ARCH_MACOSX)
 #  include "QtCore/qatomic_macosx.h"
 #elif defined(QT_ARCH_PARISC)

src/corelib/thread/qbasicatomic.h

@@ -52,6 +52,8 @@
 #  include <QtCore/qatomic_arm.h>
 #elif defined(__i386) || defined(__i386__)
 #  include <QtCore/qatomic_i386.h>
+#elif defined(__ia64) || defined(__ia64__)
+#  include "QtCore/qatomic_ia64.h"
 #elif defined(__mips) || defined(__mips__)
 #  include "QtCore/qatomic_mips.h"
 #elif defined(__x86_64) || defined(__x86_64__) || defined(__amd64)