Port the MIPS atomics to the new QBasicAtomicXXX architecture
The LL/SC instructions are only present on MIPS II and up, so don't pretend to support MIPS I. The previous implementation emitted the instructions by telling the assembler to change instruction sets. Now, the user must pass an -march= option to GCC telling it which architecture or processor is being targetted. On MIPS64, the 64-bit implementation allows supporting for long long too. Change-Id: I6dae6f8f61e563aba6a663227d91c5ddf554aa6a Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>bb10
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@ -62,8 +62,6 @@ QT_BEGIN_HEADER
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# include "QtCore/qatomic_ia64.h"
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#elif defined(QT_ARCH_MACOSX)
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# include "QtCore/qatomic_macosx.h"
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#elif defined(QT_ARCH_MIPS)
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# include "QtCore/qatomic_mips.h"
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#elif defined(QT_ARCH_PARISC)
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# include "QtCore/qatomic_parisc.h"
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#elif defined(QT_ARCH_POWERPC)
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@ -52,6 +52,8 @@
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# include <QtCore/qatomic_arm.h>
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#elif defined(__i386) || defined(__i386__)
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# include <QtCore/qatomic_i386.h>
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#elif defined(__mips) || defined(__mips__)
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# include "QtCore/qatomic_mips.h"
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#elif defined(__x86_64) || defined(__x86_64__) || defined(__amd64)
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# include <QtCore/qatomic_x86_64.h>
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#else
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